1. Technical Field
The present invention relates in general to integrated circuitry and, in particular, to integrated circuits including multiple memory arrays. Still more particularly, the present invention relates to the aggregation of detected failures across multiple memory arrays and the application of a common repair solution to all of the multiple memory arrays.
2. Description of the Related Art
As integrated circuit technology has advanced, the complexity and density of circuit devices formed within a single integrated circuit (IC) has increased dramatically. Consequently, several problems have arisen with regard to testing ICs. For example, while the conventional methodology for testing a memory array within an IC may be relatively straight forward,
ICs typically have far fewer I/O pins available to an external circuit tester than are required to adequately test the memory array.
A general solution to the above-described and other difficulties with external testing is to imbed test circuitry within an IC itself. Such integrated testing facilities are frequently referred to as built-in self-test (BIST), array self-test (AST), or array built-in self-test (ABIST) circuits and will hereinafter be referred to generically as BIST circuits.
Although the integration of BIST circuits within ICs facilitates IC testing, a central concern associated with BIST circuits is the large amount of die size consumed by the BIST circuit and associated circuitry. This concern is magnified as the number of memory arrays and other subcircuits integrated within an IC that require BIST testing multiply. This concern is particularly significant for state-of-the-art integrated circuits, such as a microprocessors and Application-Specific Integrated Circuits (ASICs), which commonly contain hundreds or thousands of relatively small memory arrays each requiring BIST testing.